1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for integrating an MPS (Merged P-i-N/Schottky) Schottky into a planar MOSFET that does not require additional masks while improving high frequency power switching, H-bridge and synchronization rectification applications, improved body diode recovery behavior leading to lower losses and less voltage oscillations in power circuits without affecting layout of the integrated MOSFET-Schottky device.
2. Description of the Related Art
In order to reduce the power consumptions and to increase the switching speed of a power semiconductor power device, it is desirable to further reduce the on-resistance and the gate capacitance. Integration of a Schottky diode in a semiconductor power device such as a metal oxide silicon field effect transistor (MOSFET) has been implemented. In addition to device configurations and manufacturing methods to integrate the Schottky diodes into trenched MOSFET devices, there is also a need to integrate the Schottky diodes into the planar MOSFET devices. The integration of the Schottky diodes into the planar MOSFET device improves the body diode recovery behavior that leads to lower losses and less voltage oscillations in power circuits. However, conventional ways of manufacturing the planar MOSFET devices with integrated Schottky diodes often require additional masks for the formation of the Schottky diodes in Schottky regions between the MOSFET cells. Therefore, higher manufacturing costs and more complicate processes are necessary for implementing the planar MOSFET device with the Schottky diodes. For this reason, there is still a need to improve the processes for manufacturing the MOSFET devices to integrate with Schottky diodes with new and improved device configurations to achieve simplified manufacturing processes.
FIGS. 1A and 1B show the standard MOSFET devices that integrate the Schottky diodes to bypass the body diode thus improving the behavior of a MOSFET device. Improvements in the MOSFET device performances enhance the H-bridge and synchronization rectification applications. Specifically, FIG. 1A shows a MOSFET with an integrated Junction Barrier controlled Schottky (JBS) area. The integrated JBS may be a Schottky diode array with a P-N junction grid interspersed between the Schottky contacts. The P-N junction will pinch-off the channel regions under the Schottky contacts to inhibit the formation of large reverse leakage current once a threshold reverse-biased voltage is applied. The shielding effect caused by the depletion layer also improves the breakdown voltage. However, there is a tradeoff that due to an increase of the series resistance. Also, since the presence of P-N junction in the integrated JBS regions takes up a large portion of surface area, for practical considerations, it may be required to reduce the overall Schottky contact areas dedicated to the forward conduction. Under that circumstance, there is an increase of the on-state forward voltage drop cause by this reduction of the overall Schottky contact area. In FIG. 1B, the integrated trench MOS barrier Schottky (TMBS) is implemented. The integrated TMBS includes Schottky diode array interspersed with MOS trench. The charge coupling between the majority charge carrier in the mesa-shaped portion of the epitaxial/drift region and the metal on the insulated sidewalls of the trenches causes a redistribution of the electric filed profile under the Schottky contact which improves the breakdown and reduces reverse leakage current.
U.S. Pat. No. 4,675,713 discloses a method of using the source Schottky junction as the body contact for a semiconductor power device. U.S. Pat. No. 4,983,535 discloses a fabrication method to manufacture a DMOS device with a source implemented with a refractory metal Schottky barrier located on top of the body region. However, these devices still have the limitations of using metals of relatively high barrier height. The device performance cannot satisfy the modern applications that require further reduction on resistance and higher drive currents.
FIG. 2 shows an improved DMOS submitted as a Application by co-inventors of this Patent Application. The DMOS has an improved configuration. Specifically, in proximity of the gate trench and adjacent to the source, there is a source-body contact trench with an anti-punch through implant disposed along the trench wall. An integrated Schottky diode is formed by depositing a high barrier height metal at the bottom of the source-body contact trench to function as the integrated Schottky contacts. A low barrier height metal is further deposited overlaying the high barrier height metal to provide ohmic contact for source and body. The DMOS device as shown in FIG. 2 provides the advantage of integrating a Schottky in every cell with no loss of die active area to form such a Schottky as in older approach. However, the high barrier height metal as required to achieve acceptable low leakage current in the off state presents a disadvantage due to the higher costs of depositing both the high barrier height metal and the low barrier height metal to meet the requirements of Schottky and source-body ohmic contact.
Additionally, the above device configurations as shown in FIGS. 1A, 1B and 2 are still limited by a breakdown vulnerability at bottom corners of the P+ pocket regions as that shown in FIGS. 1C and 1D. The breakdown vulnerability at the bottom corners at the body type dopant (P+ pocket) regions is due to a small radius of a curvature at the junction near the bottom corners of the P+ pocket regions. Furthermore, there is an abrupt dopant distribution reversal profile as that shown in FIG. 1D. FIG. 1D compares the variation of the doping profile in the JBS P+ pocket region to the doping profile in the MOSFET P body regions along two vertical lines A-A′ and B-B′ shown on FIG. 1C.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the semiconductor power devices. such that the above discussed problems and limitations can be resolved.